1. Field of the Invention
This invention relates to a method for planarizing the interface of polysilicon and, more particularly, to a method of planarizing the surface of polysilicon purge to improve the planarity of the interface of polysilicon by regulating the process temperatures in different stages.
2. Description of the Prior Art
The "single transistor DRAM cell" of a dynamic random access memory (DRAM) is composed of a MOS transistor and a capacitor. As illustrated in FIG. 1, principally, a MOS transistor comprises three electrodes, which are gate 40, source 20 and drain 30 on a semiconductor substrate 10. The conventional MOS transistors are made of metal, silicon dioxide and silicon substrate, but due to the poor adhesion ability of most metal to silicon dioxide, the current manufacturing process prefers to replace metal with polysilicon which has a better adhesion ability. However, polysilicon has a higher resistivity even after doping, so the addition of metal silicide which has a better conductivity will keep good operation state by polycide structure, in which the additional silicide has a comparable thickness with polysilicon. This typical improved gate structure composed of polysilicon and silicide is shown in FIG. 1. The prevalent silicide used in semiconductor manufacturing are tungsten silicide (WSi.sub.x), titanium silicide (TiSi.sub.x), molybdenum silicide (MoSi.sub.x), and cobalt silicide (CoSi.sub.x), in which the most favorite one is tungsten silicide (WSi.sub.x). In present, the common way to deposit tungsten silicide is by low-pressure chemical vapor deposition (LPCVD) or sputtering.
In the current commercial manufacturing process of integrated circuits, polysilicon is preferably deposited by heating then decomposing silane by the way of LPCVD. And one of the most popular ways is tubular type LPCVD, in which the deposition temperature is controlled between 400.degree. C. and 850.degree. C. and the pressure is between some torrs to 100 torr. Then the steps of nitrogen purging which is used to remove the dangerous reactant gases or inert gas in furnace and vacuuming are followed with.
To reduce the resistivity, performing doping to polysilicon is necessary to transfer it into a good electric conductor. The dopants used can be the elements in group III, such as boron, or which in group V, such as phosphorus. Nevertheless, as the impurity will penetrate into polysilicon during the process of in-situ polysilicon deposition, outgassing of impurity after vacuuming will turn out pollution in furnace and degrade the integrated circuits. Therefore, an additional layer of undoped polysilicon 43 is deposited after the deposition of doped polysilicon 42 to prevent impurity outgassing problem as shown in FIG. 1. The undoped polysilicon layer 43 also can keep from watermark formation in the following wet cleans to improve integration issues.
FIG. 2 depicts the process temperatures in different stages when depositing polysilicon. At first, stage 1 represents the period when a lot of wafers are loaded into the furnace, then in stage 2 temperature is raised from the standby temperature T.sub.1 to a preferred polysilicon deposition temperature T.sub.2. After that, polysilicon is deposited and doped at the temperature of T.sub.2, represented in stage 3, and when the desired thickness of polysilicon has been obtained, the dopant source is turned off. Next, a thin undoped polysilicon film 43 is deposited over the doped polysilicon 42 in stage 4. Then stop depositing and perform purging and de-vacuuming, in stage 5A. In stage 6A, temperature is slowly going down to standby temperature T.sub.1 just after stage 5A. Finally in stage 7, the wafers are unloaded from the furnace, thus the deposition of polysilicon is altogether completed.
However, according to the prior art, the undoped polysilicon 43 still stays in high temperature for a little while after being well deposited, as represented in stage 5A. During the process of purging and de-vacuuming with a high temperature, the layer 43 will receive the heat from the furnace and start to crystallize which is just like under an annealing process. So that a rough and uneven surface of polysilicon layer 43 is caused by the movement and recrystallization of silicon atoms on surface. Further, the peeling of tungsten silicide 44 which is subsequently deposited will be occurred due to its poor adhesion to the rough surface of polysilicon layer 43. Thus, the problem in electric property and reliability of products are unavoidable. To solve this issue and enhance the yield, a method for planarizing the surface of polysilicon is provided in the present invention to form an undoped polysilicon layer with a smooth surface by regulating the process temperatures.